module trans_phy (input				rst,
                  input				clk_10M,
                  input				clk_100M,
                  input				tx_vld,
                  input				tx_done,
                  input	[7:0]		tx_data,
                  input				ki,
                  output			tx_out);
                  
    reg			    tx8b10b_vld;
    wire	[9:0]   enc_data_out;
    
    always@(posedge clk_10M)
        if (rst)
            tx8b10b_vld <= 0;
        else
            tx8b10b_vld <= tx_vld ;
    
    enc_8b10b_s  enc_8b10b_s_inst
    (
    .clk_10M			(clk_10M),
    .rst				(rst),
    .ki				    (ki),
    .data_in			(tx_data),
    .data_out		    (enc_data_out)
    );
    
    lvds_tx_pack   lvds_tx_pack_inst
    (
    .rst				(rst),
    .clk_10M			(clk_10M),
    .clk_100M		    (clk_100M),
    .tx_vld			    (tx8b10b_vld),
    .tx_in			    (enc_data_out),
    .tx_done			(tx_done),
    .lvds_out		    (tx_out)
    );
    
endmodule
